MIPS (32-bit)

1. Delay slots

MIPS Architectureusers.cs.duke.edu

In the MIPS architecture, control-flow instructions such as branches and jumps have an architectural delay slot. This means that the instruction immediately following a branch or jump is always executed, regardless of whether the branch is taken or where the jump transfers control

This behavior exists due to the MIPS pipeline design, where the instruction following a control-flow change has already been fetched and is allowed to complete execution before the program counter (PC) is updated

As a result, the branch or jump instruction and its delay slot instruction are executed as a pair. This means that the branch condition or jump target is resolved first before the delay slot instruction executes, and only then does the control flow change

Example

Given the following assembly snippet:

41f990:       10400022        beqz    v0,41fa1c <get_merge_ipaddr@@Base+0x12c>
41f994:       02202021        move    a0,s1
41f998:       0320f809        jalr    t9
41f99c:       00402821        move    a1,v0

Execution flow for beqz

• At address 0x41f990, the instruction tests whether register v0 is zero:

beqz v0, 41fa1c

• The instruction immediately following it at 0x41f994 is the delay slot instruction for the branch:

move a0, s1

Execution behavior

1. The branch condition (v0 == 0) is evaluated

2. The delay slot instruction at 0x41f994 executes unconditionally

3. If v0 == 0, execution continues at 0x41fa1c. Else, execution falls through to 0x41f998

Thus, move a0, s1 executes regardless of whether the branch is taken

Execution flow for jalr

• At address 0x41f998, the instruction performs an indirect function call, saving the return address in ra:

jalr t9

• The instruction immediately following it at 0x41f99c is the delay slot instruction for the jump:

move a1, v0

Execution behavior

1. The return address is written to ra

2. The delay slot instruction at 0x41f99c executes unconditionally

3. Control is transferred to the address contained in register t9

As a result, move a1, v0 executes before the target function is called

2. Base + offset addressing

MIPS Addresseswww.eecis.udel.edu

lw   d,off(b)       # $d <-- Word from memory address b+off
                    # b is a register. off is 16-bit two's complement.

Register d will contain the value from memory address b+off